|
|
|
An Integrated Software Environment to Design Polymorphic Fault Tolerant Processors for Command and Control Functions on RadHard FPGAs
|
|
|
| Commercial FPGA (field programmable gate arrays) have started making a powerful impact on space science missions, owing to the success of their deployment on the Mars rovers. They offer highly adaptable/reconfigurable electronic fabrics which if efficiently utilized can outperform the traditional monolithic microprocessors for on-board processing. The thrust in deploying autonomous command and control (C&C) software on-board, driven by sophisticated scheduling and navigation algorithms, has created a need for highly adaptable and computationally powerful on-board processing systems. It is expected that for tasks such as orbital rendezvous and atmospheric entry, the processing rates and states of underlying kalman filters rapidly increase as compared to more mellow times of the missions. This requires the on-board computing systems to quickly change their capabilities at run time. FPGAs offer the ability to host such adaptable processing systems, but the onus is on the user to design such systems. In order to create systems that can be adapted quickly to (i) a new mission, or (ii) a new processing speed for a different task on the same mission, or (iii) a variant of a computation algorithm due to change in health of the spacecraft (in a fault tolerant manner), the circuits need to be (a) polymorphic and (b) tailored well to the data/control flow nature of the application. In this project, we propose to capture the data/control flow nature of C&C applications by first compiling their C/C++ programs into machine independent Intermediate Representation (IR) forms. Then, through a set of feature extraction compiler passes, we will extract their core data/control flow patterns. These patterns will act as templates to soft macros that will form the core of the data-paths and state machines on an FPGA. We will grow polymorphic architectures in the Viva design language, on top of these soft-macros (which act as seed elements). These architecture modules will be capable of order tensor, information rate and data type polymorphism. To provide strong fault tolerance capabilities in these modules, we will embed triple modular redundancy and built in self test features at the seed element level. To provide a higher degree of freedom in programmability of the overlaying architecture, we will partition the application�s architecture into a group of soft microprocessors on the FPGA. This will permit us to partition and compile the application�s C/C++ programs onto the custom instruction sets of the soft microprocessors. In this project we will integrate state of the art technologies and tools for code generation of mission/planning & state estimator algorithms, FPGA synthesis tools and compilers, into a single design environment. Through this system we will be able to provide a cost effective and time saving design environment for NASA engineers and scientists for future space missions. |
|
|
